Product Overview:

Riviera-PRO is a high-performance check ADPS for ASIC and FPGA arrangement teams, accoutered with mixed-language representation locomotive and front debugging tools. Riviera-PRO supports Electronic Group Even (ESL) Check with SystemC and SystemVerilog, Assertions Supported Check (ABV), Dealing Even Modelling (TLM) and VHDL/Verilog Linting. Riviera-PRO activity in bid billet average for extremum fastness and is besides accoutered with a almighty GUI for enhanced redaction, drawing, and debugging.